1. Field of the Invention
The present invention generally relates to memory circuits, and more particularly, the present invention relates circuits and methods for isolating memory cells of a memory device.
2. Description of the Related Art
A conventional memory device, such as a dynamic random access memory (DRAM) device, is schematically illustrated in FIG. 1. As shown, a plurality of memory cell arrays 10 and sense amplifiers 20 are alternately arranged. Each memory cell array 10 is associated with a row decoder 30 which generates word line signals (WL) for selection of word lines of the corresponding memory cell array 10. Likewise, a column decoder 50 generates column select signals (CSL) for selection of bits lines of the memory cells arrays 10. Also, as shown, each sense amplifier 20 is controlled by control signals (CONTROL) generated by respective a control circuit 40.
The memory device of FIG. 1 is characterized by the sharing of each sense amplifier 20 between two adjacent memory cell arrays 10. Isolation circuitry contained in each sense amplifier 20 is utilized to isolate one of the adjacent memory cell arrays 10 while the sense amplifier 20 is being used in conjunction with the other of adjacent memory cell arrays. This is explained in more detail with reference to the circuit diagram of FIG. 2.
Referring to FIG. 2, a sense amplifier region is operatively connected between a first memory cell array block 1 (BLOCK1) and a second memory cell array block 2 (BLOCK2). Each block contains complimentary memory cells C0 and C1 connected between source voltage VP and complimentary bit lines BLn and BLBn (where n=0, 1, 2, . . . ), respectively. A column decoder 50 receives a pre-decoded column address signal DCA and generates corresponding column select signals CSLn for selection of the complimentary bit lines BLn and BLBn. Also, as shown, the complimentary memory cells C0 and C1 are respectively read/write enabled by word lines WL0 and WL1 (or word lines WL510 and 511), which in turn are connected to a row decoder 30 which decodes pre-decoded row address signals DRA. As one skilled in the art will appreciate, FIG. 2 only shows a small portion of a typical memory block, and in reality each memory block includes numerous pairs of word lines and bit lines connected to numerous pairs of complimentary memory cells.
The sense amplifier region of FIG. 2 includes equalization transistors E1, E2 and E3 which form an equalization circuit connected as shown between each pair of bit lines BL0 and BLB0. This equalization circuit is responsive to an equalization control signal PEQL (or PEQR) generated by an equalization control signal generator 41 (PEQL GEN. and PEQR GEN.) to equalize, or pre-charge, the bit lines BL0 and BLB0 to VCC/2 (=VBL). Generally, this is done prior to accessing (e.g., reading) the memory cells connected to the bit lines.
Transistors P1, P2 and N1, N2 are connected as shown to form a sense amplifier which functions in a well know manner to amplify a voltage differential across the bit lines BL0 and BLB0. The sense amplifier is enabled by sense enable voltages LA and LAB generated by amplification voltage generators 43 and 44 (LA GEN. and LAB GEN.).
Transistors S1 and S2 are isolation transistors which are responsive to isolation control signals PISOL and PISOR generated by an isolation control signal generator 42 (PISOL GEN. and PISOR GEN.) in response to block selection signals PBLOCK1 and PBLOCK2. The isolation transistors S1 and S2 are controlled to selectively isolate one of the blocks 1 or 2 while the sense amplifier is being used for the other of the blocks 1 or 2.
Transistors L1 and L2 are column select transistors which are used to selectively couple the bit lines BL0 and BLB0 to input/output lines IO and IOB, respectively. These transistors L1 and L2 are activated in response to the column select signals generated by the column decoder 50. For example, column select signal CSL0 controls coupling of the bit lines BL0 and BLB0 to the input/output lines IO and IOB, column select signal CSL1 controls coupling of the bit lines BL1 and BLB1 to the input/output lines IO and IOB, and so on.
FIG. 3 is a block diagram for explaining the generation of the word line signals WL and the column select signals CSL. Externally supplied command and address signals are applied to terminals of the memory device as shown. A command decoder 60 is response to the command signals to generate a row access master signal PR and a column access master signal PC. An address buffer 70 receives the externally supplied address, and outputs a row address RA and a column address CA according to the externally supplied address and the row and column access master signals PR and PC. Pre-decoders 80 and 85 convert the row and column address signals RA and CA to pre-decoded row and column address signals DRA and DCA, respectively. These pre-decoded signals are then decoded by main decoders 90 and 95 to generate the word line signal WL and the column select signal CSL, respectively.
FIG. 4 is a schematic block diagram showing the generation of the isolation control signals, the equalization signals, and the sense enable signals of the memory device shown in FIG. 2. As described above in connection with FIG. 3, the pre-decoder 80 outputs pre-decoded row address signals DRA. Bits DRAij of the pre-decoded row address signal DRA are applied to the main decoder 90 which, as described above, outputs a corresponding word line signal WL. The remaining bits DRAkl of the pre-decoded row address signal DRA (typically, the most-significant bits of DRA) are used for block selection and applied to the block generator 100. The block generator 100 outputs a block selection signal PBLOCK1,2 which is indicative of one of the two memory array blocks 1 and 2 of the memory device. Although two blocks are described in this example, the memory device may include many more memory array blocks (e.g., 16 or more).
Still referring also to FIG. 4, the isolation control signal generator 42 controls isolation control signals PISOL and PISOR in accordance with the block selection signal PBLOCK1,2. Likewise, the equalization control signal generator 41 controls equalization control signals PEQL and PEQR in accordance with the block selection signal PBBLOCK1,2.
Meanwhile, the sense control circuit 110 of FIG. 4 outputs a sense enable master signal PS in accordance with the row access master signal PR (see FIG. 3) and the row address signal bits DRAij or DRAkl. The sense enable master signal PS is received by sense amplifier control circuits 120 and 130, which respectively output sense amplifier control signals PS_PSA and PS_NSA. These control signals PS_PSA and PS_NSA are used to respectively control the voltage level of the sense enable voltages LA and LAB illustrated in FIG. 2 (see, e.g., FIG. 9 discussed below).
FIG. 5 is an exemplary circuit diagram of the isolation control circuit generator 42 illustrated in FIG. 4, and FIG. 6 is a logic table of the same. Generally, at least one of the block signals PBLOCK1 and PBLOCK2 is isolation enabled (Low) at all times. Here, isolation enabled means that the corresponding memory block is isolated from the sense amplifier. As is apparent from FIG. 5, and as shown in the table of FIG. 6, when PBLOCK1 is enabled (Low) and PBLOCK2 is non-enabled (High), isolation signal PISOL becomes VSS (Low) and isolation signal PISOR becomes VPP (High). As such, referring to FIG. 2, the cell array block 1 is isolated from the sense amplifier circuitry, while cell array block 2 is coupled to the sense amplifier circuitry. In contrast, when PBLOCK1 is non-enabled (High) and PBLOCK2 is enabled (Low), isolation signal PISOL becomes VPP (High) and isolation signal PISOR becomes VSS (Low). Thus, the cell array block 1 becomes coupled to the sense amplifier circuitry, and cell array block 2 is isolated from the sense amplifier circuitry. When both PBLOCK1 and PBLOCK2 are non-enabled (Low), for example during a standby mode, then the circuit block identified by reference number 150 functions to pre-charged and equalized PISOL and PISOR to voltage VCC.
FIG. 7 is a simplified circuit diagram for explaining a charge sharing operation of a conventional memory device. The bit lines BL and BLB of the device include pre-charged capacitors CBL_CELL and CBL_SA (CBLB_CELL and CBLB_SA). As examples, CBL_CELL is about 3 times the size of CCELL of the memory cell, and CBL_CELL is greater than the size of CBL_SA of the sense amplifier. In operation, assume the capacitor of memory cell C0 contains a data “1”. When the word line WL is enabled, the charges stored in the various capacitors of bit line BL are “shared” as depicted by the two-headed arrow. The result is a small increase (e.g., 100 mV or more) in the voltage of bit line BL which is to be detected by the sense amplifier.
FIG. 8 is a timing diagram of the charge sharing operation of the circuit of FIG. 5, again in the case where cell C0 contains data “1”. In an isolation (ISO) activation period, isolation control signal PISOL is increased from VCC to VPP, and isolation control signal PISOR is decreased from VCC to VSS. At the end of the ISO activation period, the voltage of word line WL is increased from VSS to VPP. As such, the capacitor CCELL becomes coupled to the bit line BL, and the resultant charge sharing operation causes the voltage of bit line BL to increase from VBL to VBL+ΔVBL. Note that the voltage of bit line BLB remains at VBL.
In order to speed up the bit line sense operation, it is generally necessary to lower the threshold voltages of the sense amplifier transistors. However, a trade-off situation arises in that lower threshold voltages result in increased leakage current, which in turn reduces an effective sense interval of the sense operation. The dashed lines shown in the circuit diagram of FIG. 9 depict sense amplifier leakage current paths in the case where bit line BL is at voltage VBL+ΔVBL, and bit line BLB is at voltage VBL. The result of this leakage is illustrated in FIG. 10. After the charge sharing operation which follows activation of the isolation control signal PISO, the voltage level of bit line BL gradually decreases as a result of the sense amplifier leakage. The line identified by circle-2 of the figure shows the bit line voltage characteristic in the case where the VCC voltage (i.e., the sense amplifier transistor thresholds) is reduced relative to that of the line identified by circle-1 of the figure. The leakage is more pronounced at lower thresholds, and accordingly, the voltage drop is more rapid. As shown, the result is a significantly reduced sensing interval. As the trend in the industry is for lower and lower VCC operating voltages, sense amplifier leakage is becoming increasingly problematic.
In the meantime, a number of bit line bridge defects tend to occur in the manufacture of the memory device. Turning now to FIG. 12, these defects are generally of two types. The first type (circle-1) results from a short or leakage between bit lines of the same bit line pair (e.g., BL0 and BLB0). The second type (circle-2) results from a short or leakage between bit lines of adjacent bit line pairs (e.g., BLB0 and BL1). As is schematically shown, the bit lines of the memory cell array are packed more densely than those in the sense amplifier regions, and accordingly, bit line bridge defects are relatively common. As such, the memory device is thoroughly tested after manufacture for the presence of bit line bridge defects, and techniques are known for replacing defective bit lines with spare bit lines.
One problem with testing for bit line bridge defects, however, is that it is becoming increasingly difficult to distinguish bit line leakage from the leakage of the sense amplifier. As mentioned above, sense amplifier leakage causes a gradual drop in ΔVBL. The leakage attended by a bit line bridge defect can similarly reduce ΔVBL. Accordingly, it has become to difficult identify bit line bridge defects, particularly in the case where low threshold sense amplifier transistors are utilized.